LZ4 Decompression IP Suite
Three production-oriented, ultra-low latency streaming cores for different fabric and bandwidth targets. Choose the implementation that fits your system constraint, then review the shared architecture, benchmark, and PPA results.
Silesia benchmark
Up to560.294MB/s
4.482 Gb/ssustained·ultra-low latency
Deliverables
Encrypted RTL, integration notes, and verification vectors
Support
30 days free email-based support included
01 · Overview
Simple streaming LZ4 decompression for FPGAs
This IP takes compressed LZ4 data in and rebuilds the original data on an FPGA. It processes the stream as data arrives, making it a strong fit for ultra-low latency paths between storage, networking, memory, or an accelerator.
Stream in, stream out
AXI4-Stream ready/valid handshaking makes the core easy to connect and safe under backpressure.
Verified output
The decompressed output matches the original data, with checks for malformed tokens, offsets, and block boundaries.
Ultra-low latency
An 11-clock design latency keeps decompressed data moving quickly through the pipeline.
Feature comparison
Compare the three LZ4 variants
All three cores use the same simple streaming interface and ultra-low latency design target. The main difference is how much logic they use to reach higher sustained bandwidth.
| Feature | LZ4 Lite | LZ4 Fast | LZ4 Turbo |
|---|---|---|---|
| Best for | Small, area-limited designs | Balanced systems | Maximum sustained bandwidth |
| AXI4-Stream input / output | 32-bit / 32-bit | 32-bit / 32-bit | 32-bit / 64-bit |
| Error detection |
|
|
|
| Ultra-low latency | 11 clocks | 11 clocks | 11 clocks |
| Peak output | Up to 4 B/clock | Up to 4 B/clock | Up to 8 B/clock |
| Fmax — AMD / Xilinx | 260 MHz | 280 MHz | 290 MHz |
| Fmax — Intel / Altera | 290 MHz | 270 MHz | 250 MHz |
| Flow control | AXI ready/valid + backpressure | AXI ready/valid + backpressure | AXI ready/valid + backpressure |
02 · Architecture
A clear, linear data path
The compressed stream moves from left to right through an ultra-low latency pipeline. The history buffer feeds match reconstruction and receives the bytes that have already been produced.
03 · PPA & Silesia benchmark
Implementation and bandwidth results
Use the tabs below to compare PPA numbers, then review the Silesia bandwidth delivered by each ultra-low latency core.
Silesia benchmark · all three variants
Measured sustained decompression bandwidth
Across the full 12-file, 57-block corpus, every variant produced byte-exact output. Choose the bandwidth profile that matches your system bottleneck.
LZ4 Lite
36.571 MB/s
Bandwidth
0.293 Gb/s
Average output
0.365706 B/clk
Capacity
9.143%
LZ4 Fast
361.284 MB/s
Bandwidth
2.890 Gb/s
Average output
3.612842 B/clk
Capacity
90.321%
LZ4 Turbo
560.294 MB/s
Bandwidth
4.482 Gb/s
Average output
5.602942 B/clk
Capacity
70.037%
04 · Verification
Verification
Verified, protocol-aware, and formally checked.
Reference check
Compared against software LZ4 output.
Corner cases
Literal, match, offset, and boundary cases.
Protocol checks
Ready/valid and backpressure behavior.
Formal verification
Formal checks completed for control and stream behavior.
Regression
Automated checks across all variants.
05 · Deliverables & support
A practical evaluation handoff
Everything needed to review, integrate, and evaluate the IP with engineering support included.
Encrypted RTL package
Controlled enterprise evaluation package.
Integration collateral
Interface notes and integration guidance.
Verification collateral
Vectors and result evidence.
30 days included
Free email-based support after delivery.